Integrated circuit (IC) process scaling is leading high-performance chip designs to higher operating frequencies, lower power supply voltages, and higher power dissipation. This poses greater challenges to design engineers not only with respect to IC design, but also for package and power supply design. The close coupling between the levels of the power system and the need to trade off power vs. performance is making dynamic power management a necessity for chip design.
Increased chip functionality results in the need for huge power distribution networks, also referred to as power grids since they typically have a grid-like structure. Lower supply voltage, on the other hand, makes the voltage variation across the power grids highly critical since it may lead to chip failures. Voltage drops on the power grid reduce the supply voltage at logic gates and transistor cells to less than ideal operating references, which leads to reduced noise margin, higher logic gate delay, and overall slower switching. Reduced noise margins may also lead to false switching at certain logic gates and latches. Higher logic gate delays, on the other hand, may slow down the circuit enough so that timing requirements cannot be met. Thus, the power grids are rapidly becoming a limiting factor in high-performance IC chips, especially, advanced microprocessor designs.
As is well known, power is transferred through many complicated circuit structures before it is delivered where it is needed. From the power supply through the printed circuit board (PCB, or board, for short), packaging, input/output (I/O) pins, die bumps (e.g., controlled collapse chip connection or C4 bumps), and on-chip power grid to the transistors, every portion of the circuitry in the power delivery path plays a crucial role in ensuring the quality of power delivered. The robustness of the power delivery network, especially the on-chip power grid, is accordingly one of the keys to successful CPU design.
There are several sources that cause the degradation of the quality of power delivery systems such as IR drop, Ldi/dt drop, and resonance issues that gain prominence at high frequencies. The IR drop is typically very small due to the low resistance of the package and power grid network, while the inductance-induced voltage drop is a major concern in the package and power grid design. Whereas the IR can be simply verified by the DC analysis, the Ldi/dt drop issues need to be analyzed by transient simulation due the time-dependent differentiation nature of Ldi/dt drop.
To ensure the design quality of power delivery, extensive AC and transient simulations are required during the design process. Typically, both the power grid and on-chip load circuitry are simulated to obtain a reliable measure of the overall power distribution characteristics of a die. In addition, to achieve even higher levels of accuracy, the package and board environment associated with the semiconductor die is also simulated. In such applications, it becomes necessary to interconnect the various subcircuit layers, which may have different levels of granularity, before a simulation can be performed.